The present invention is directed to memory circuits, and more particularly to random access memories having multiple read and/or write ports.
Recently, random access memories (RAMs) having multiple input and/or output ports for each cell in the memory have gained increasing interest. The various ports can be simultaneously accessed, thereby enabling data flow to multiple locations to be accomplished at a faster rate. Because of the increased operating speed that multiple port RAMs provide, they are highly desirable for use in computational intensive systems, such as signal and image processing, work stations and computer-aided design (CAD) terminals. In addition to the increased throughput multi-port RAMs provide in such systems, they allow the overall design of the system to be simplified.
In the past, multiple port RAMs have been implemented with CMOS technology. See, for example, Dedrick, "Multi-Port Register File Streamlines Signal Processing," EDN, Nov. 15, 1984, pp. 301-306 and Dedrick, "Multi-Port Register File Simplifies and Speeds Digital Signal Processing," Electronic Design, May 17, 1984, pp. 213-222. Generally speaking, the design principles of CMOS technology facilitate the implementation of multi-port RAMs. Furthermore, CMOS technology is desirable because of its low power requirements.
However, one limitation associated with CMOS memory circuits is the slower operating times that they exhibit, relative to memory circuits implemented with bipolar technology. Generally, the operating speed of a bipolar RAM is at least an order of magnitude greater than the speed of a CMOS RAM. For certain applications requiring high speed access to the memory, a bipolar multiple port RAM circuit would be desirable. To date, however, RAMs that have been implemented in bipolar technology have provided a limited number of input and output ports. Most offer only single or dual ports. A 5-port register file using ECL technology is described in Rose, "A Sub 10 ns Bipolar 5 Port 1 kbit Register File", 1986 Bipolar Circuits and Technology Meeting, IEEE 1986, pp. 95-95. While offering more than two ports, the approach described in this paper requires a relatively high component count per layout area and consumes a significant amount of power.